Methods of forming conductive metal silicides by reaction of metal with silicon

ABSTRACT

The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

TECHNICAL FIELD

This invention relates to methods of forming conductive contacts tosource/drain regions of field effect transistors, and to methods offorming local interconnects.

BACKGROUND OF THE INVENTION

Integrated circuitry includes a plurality of different type ofelectronic components or devices, some of which electrically connectwith one another and others of which are electrically isolated from oneanother. By way of example only exemplary devices include field effecttransistors, capacitors and conductive lines. Field effect transistorsare commonly composed of a pair of source/drain regions having aswitchable channel region formed therebetween which is controlled by aconductive gate. Conductive electrical contact is typically made to oneor both of the source/drain regions to connect the transistor with otherintegrated circuitry devices.

Conductive lines, for example transistor gate lines, can extend or runglobally over large areas of a substrate comprising the integratedcircuitry. Some conductive lines are much shorter and associated withvery small portions of integrated circuitry, and are typically referredto as local interconnects. For example, and by way of example only, somelocal interconnects electrically connect source/drain regions ofdifferent field effect transistors. Further by way of example only, somelocal interconnects electrically connect a source/drain region of onetransistor with a gate of another transistor. Further by way of exampleonly, local interconnects are utilized to connect different conductivenode regions of the integrated circuitry which do not necessarilyconstitute any portion of a field effect transistor.

While the invention was motivated in addressing the above identifiedissues, it is in no way so limited. The invention is only limited by theaccompanying claims as literally worded, without interpretative or otherlimiting reference to the specification, and in accordance with thedoctrine of equivalents.

SUMMARY

The invention comprises methods of forming a conductive contact to asource/drain region of a field effect transistor, and methods of forminglocal interconnects. In one implementation, a method of forming aconductive contact to a source/drain region of a field effect transistorincludes providing gate dielectric material intermediate a transistorgate and a channel region of a field effect transistor. At least some ofthe gate dielectric material extends to be received over at least onesource/drain region of the field effect transistor. The gate dielectricmaterial received over the one source/drain region is exposed toconditions effective to change it from being electrically insulative tobeing electrically conductive and in conductive contact with the onesource/drain region.

In one implementation, a method of forming a local interconnect includesproviding gate dielectric material intermediate a transistor gate and achannel region of a field effect transistor over a semiconductorsubstrate. At least some of the gate dielectric material extends to bereceived between first and second node regions of the semiconductorsubstrate. The gate dielectric material received between the first andsecond node regions is exposed to conditions effective to change it frombeing electrically insulative to being electrically conductive and alocal interconnect is formed from the changed material whichelectrically connects the first and second node regions.

In one implementation, a method of forming a local interconnect includesproviding capacitor dielectric material proximate a first capacitorelectrode over a semiconductor substrate. At least some of the capacitordielectric material extends to be received between first and second noderegions of the semiconductor substrate. The capacitor dielectricmaterial received between the first and second node regions is exposedto conditions effective to change it from being electrically insulativeto being electrically conductive and a local interconnect is formed fromthe changed material which electrically connects the first and secondnode regions.

Other aspects and implementations are contemplated.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

FIG. 1 is a diagrammatic cross section of a substrate fragment inprocess in accordance with an aspect of the invention

FIG. 2 is a view of the FIG. 1 substrate at a processing step subsequentto that depicted by FIG. 1.

FIG. 3 is a view of the FIG. 2 substrate at a processing step subsequentto that depicted by FIG. 2.

FIG. 4 is a view of the FIG. 3 substrate at a processing step subsequentto that depicted by FIG. 3.

FIG. 5 is an alternate view to that of FIG. 4 of the FIG. 3 substrate ata processing step subsequent to that depicted by FIG. 3.

FIG. 6 is another alternate view to that of FIG. 4 of the FIG. 3substrate at a processing step subsequent to that depicted by FIG. 3.

FIG. 7 is a view of the FIG. 6 substrate at a processing step subsequentto that depicted by FIG. 6.

FIG. 8 is a view of the FIG. 4 substrate at a processing step subsequentto that depicted by FIG. 4.

FIG. 9 is a diagrammatic cross section of a substrate fragment inprocess in accordance with an aspect of the invention.

FIG. 10 is a diagrammatic top plan view of a substrate fragment inprocess in accordance with an aspect of the invention.

FIG. 11 is a view taken through line 11-11 in FIG. 10.

FIG. 12 is a view of the FIG. 10 substrate at a processing stepsubsequent to that depicted by FIG. 10.

FIG. 13 is a view taken through line 13-13 in FIG. 12.

FIG. 14 is a view of the FIG. 11 substrate in process in accordance withan aspect of the invention.

FIG. 15 is a diagrammatic cross section of a substrate fragment inprocess in accordance with an aspect of the invention.

FIG. 16 is a view of the FIG. 15 substrate at a processing stepsubsequent to that depicted by FIG. 15.

FIG. 17 is a diagrammatic cross section of a substrate fragment inprocess in accordance with an aspect of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8).

By way of example only, exemplary preferred implementations of methodsof forming a conductive contact to a source/drain region of a fieldeffect transistor are initially described with reference to FIGS. 1-9.Referring initially to FIG. 1, a semiconductive substrate fragment isindicated generally with reference numeral 10. In the context of thisdocument, the term “semiconductor substrate” “or semiconductivesubstrate” is defined to mean any construction comprising semiconductivematerial, including, but not limited to, bulk semiconductive materialssuch as a semiconductive wafer (either alone or in assemblies comprisingother materials thereon), and semiconductive material layers (eitheralone or in assemblies comprising other materials). The term “substrate”refers to any supporting structure, including, but not limited to, thesemiconductive substrates described above. In the depicted exemplarypreferred embodiment, fragment 10 comprises bulk semiconductivesubstrate material 12, for example monocrystalline silicon, havingtrench isolation oxide regions 14 formed therein. Of course,semiconductor-on-insulator circuitry fabrication, as well as othercircuitry fabrication whether existing or yet-to-be developed, is alsocontemplated. Exemplary materials for trench isolation regions 14include one or both of silicon dioxide and silicon nitride.

Substrate fragment 10 comprises a field effect transistor 16 infabrication. Such is depicted as comprising source/drain regions 18 and20, and a channel region 22 therebetween in fabrication withinsemiconductive material 12. A transistor gate construction 24 isreceived operably proximate channel region 22, with a gate dielectricmaterial 26 being provided over semiconductor substrate 12/14intermediate transistor gate construction 24 and channel region 22. Byway of example only, gate construction 24 is depicted as comprising aconductive transistor gate portion 28 comprised of two conductivelayers, for example a metal or metal silicide layer 30 received overconductively doped polysilicon 32. Gate construction 24 is also depictedas comprising insulative sidewall spacers 34 and an insulative cap 36,for example comprised of silicon nitride. The depicted construction isexemplary only, and of course, other constructions are contemplated(whether existing or yet-to-be developed), and further by way of exampleonly, the exemplary spacers and insulative cap (if used) might not befabricated at this portion in the process. Further, at this point in theprocess, source/drain regions 18 and 20 (and channel 22) might or mightnot be effectively conductively doped with a conductively enhancingimpurity, and further by way of example only, might constitute elevatedsource/drains and/or conductive metal and/or conductive metal compounds.In the depicted example, field effect transistor 16 is formed over asemiconductor substrate 12/14 and is oriented generally horizontallyrelative thereto, although of course other orientations arecontemplated.

At least some of gate dielectric material 26 extends to be received overat least one of source/drain regions 18 and 20 of field effecttransistor 16, with material 26 extending to be received over both suchsource/drain regions in the depicted example. Further in the exemplarypreferred embodiment, all of the elevational thickness of gatedielectric material 26 extends to be received over the source/drainregion or regions. An exemplary preferred thickness range for gatedielectric material 26 is from 5 Angstroms to 100 Angstroms. Preferably,extending gate dielectric material 26 is a high k dielectric materialhaving a dielectric constant of at least 8. By way of example only,preferred gate dielectric materials 26 include metal oxides, for exampleany one or a combination of hafnium oxide, aluminum oxide, tantalumoxide, zirconium oxide and titanium oxide (and including silicates ofhafnium, aluminum, tantalum, zirconium and titanium), to name a few.Other gate dielectric materials are, of course, also contemplated, andwhether existing or yet-to-be developed. For purposes of the continuingdiscussion, gate dielectric material 26 can be considered as having anextending portion 31 received over source/drain region 20.

Referring to FIG. 2, a dielectric layer 38 has been formed overtransistor gate 16 and source/drain regions 18 and 20. By way of exampleonly, discussion proceeds with respect to the one source/drain region 20for the formation of a conductive contact thereto, although alternatelyor likely in addition thereto a conductive contact would also be made tosource/drain region 18. Exemplary preferred materials for dielectriclayer 38 include one or a combination of doped and undoped oxides, forexample silicon dioxide and borophosphosilicate glass (BPSG) andphoshosilicate glass (PSG).

Referring to FIG. 3, a contact opening 40 has been formed intodielectric layer 38 to extending portion 31 received over source/drainregion 20 of extending gate dielectric material 26. By way of exampleonly, such can be formed by photolithographic patterning and etch.Extending portion 31 might function as an etch stop in forming contactopening 40.

Referring to FIG. 4, extending portion 31 of gate dielectric material 26received over source/drain region 20 has been exposed to conditionseffective to change it from being electrically insulative to beingelectrically conductive and in conductive contact with source/drainregion 20. By way of example only, the exposing might be effective toform extending material 31 to be transformed to one or both of anelemental metal and/or a conductive metal compound. By way of exampleonly, exemplary metal compounds include conductive metal nitrides,conductive metal borides, conductive metal suicides, conductive metaloxides, conductive metal carbides, conductive metal halides andconductive metal sulfides. Further by way of example only, such exposingmight include plasma, or alternately be void of exposure to plasma.Further, such exposing might include ion implantation with or without(or in combination with) plasma exposure. Further by way of example onlywhere plasma exposure is utilized and where the extending gatedielectric material comprises a metal oxide, the plasma exposure mightcomprise at least some exposure to a reaction-inert material whichbreaks metal-oxygen bonds of the metal oxide to facilitatetransformation to a conductive material, for example exposure to anargon and/or H₂ and/or other reducing gas-comprising plasma. For ionimplantation, exemplary ion implantation species include H, N, Ar, H₂,NH₂ ⁺, B plus H, and BF₂ plus H, and/or elements and/or compounds withhigher affinity that the matrix metal or material (I.e., Ru, Ir) whichcan facilitate the breaking of metal-oxygen bonds, drive oxygen from thelayer and transform the material to one or both of elemental metal or aconductive metal compound.

By way of example only, the above exemplary preferred metal oxidedielectric materials might be transformed to conductive metal nitrides,conductive metal borides or conductive elemental metals of the metaloxides. For example, exposure of such materials to a nitrogen containingatmosphere (N₂ and/or NH₃), preferably including plasma species thereofat a preferred temperature range of from 500° C. to 900° C. and at apreferred pressure range of from 1 mTorr to atmospheric and abovepressures, can be utilized to form conductive metal nitride (i.e., HfN,TaN, AlN and/or TiN) extending portions 31. If a hydrogen species, forexample H₂, were utilized in place of N₂ or NH₃, the exposure could beconducted for a time period effective to reduce the metal oxides all theway back to there elemental metals, including alloys thereof (i.e., Hf,Ta, Al and/or Ti). Exemplary exposure to B₂H₆ could be utilized to formconductive metal borides. Further by way of example only, the exposingcould include forming the extending material to comprise an elementalmetal followed by exposure to a reactive one of a nitride and/or boroncontaining material to form a conductive metal nitride and/or conductivemetal boride.

Further by way of example where a silicide is desired to be formed, suchmight result from one or both of exposure to a silicon comprisingatmosphere, and/or from the reaction of metal of the extending gatedielectric material with silicon of the one source/drain region wheresuch comprises silicon.

FIG. 4 depicts forming extending material 31 to be homogeneous. By wayof example only, FIG. 5 depicts an alternate exemplary embodimentsubstrate fragment 10 a. Like numerals from the first describedembodiment are utilized where appropriate, with differences beingindicated with the suffix “a” or with different numerals. FIG. 5 depictsextending material 31 a as not being homogeneous, and comprising a firstconductive outer material 41 and a different conductive inner material43. By way of example only, material 41 might comprises a conductivemetal nitride with material 43 comprising a conductive metal silicide,for example formed by any of the above-described methods. Of course,combinations of elemental metals (which include alloys thereof) andconductive metal compounds (including conductively doped semiconductivematerials) are also contemplated.

The exposing of gate dielectric material received over source/drainregion 20 to change it from being electrically insulative to beingelectrically conductive also preferably, by way of example only,includes methods as described in our co-pending U.S. patent applicationSer. No. 10/822,118, filed Apr. 8, 2004, entitled “Methods of Forming aReaction Product and Methods of Forming a Conductive Metal Silicide byReaction of Metal with Silicon”, listing Gurtej S. Sandhu and Guy T.Blalock as inventors, and filed under attorney docket number M122-2268,the application of which is herein fully incorporated by reference.Exemplary preferred methods are, by way of example only, described withreference to FIGS. 6 and 7 with respect to a substrate fragment 10 b.Like numerals from the first described embodiment are utilized whereappropriate, with differences being indicated with the suffix “b” orwith different numerals. FIG. 6 depicts the deposition of anothermaterial 42 over extending gate dielectric material 31, with suchanother material being different in composition from that of extendinggate dielectric material 31. By way of example only where gatedielectric material 26/31 comprises a metal oxide, exemplary materials42 include Ti, Ta, and Ru. Pursuant to the patent applicationincorporated by reference, extending gate dielectric material 31 and theother material 42 can be considered as being received proximate oneanother at an interface 44 which, in the depicted preferred embodiment,is in a contacting relationship, although such is not required inaccordance with the application incorporated by reference. Extendinggate dielectric material 31 and the another material 42, as beingproximate one another at interface 44, are capable of reacting with, oneanother at some minimum reaction temperature when in an inert non-plasmaatmosphere at a pressure. Interface 44 is provided at a processingtemperature which is at least 50° C. below the minimum reactiontemperature and at the pressure.

Referring to FIG. 7, and with interface 44 (not shown) at the processingtemperature and at the pressure, substrate 10 b has been exposed to aplasma effective to impart a reaction of extending gate dielectricmaterial 31 with the another material 42 to form a reaction productthird material 31 b which is in conductive contact with source/drainregion 20. The application incorporated by reference did not transformall of the underlying material to a new material. However and by way ofexample only, increasing the processing time, temperature, pressure,plasma and/or ion implantation dose or energy intensity, including anycombinations thereof, can be conducted effective to transform all of theunderlying gate dielectric material 26 extending to over source/drainregion 20 to be transformed to a conductive material. Preferredattributes and other aspects are otherwise preferably as described inthe application incorporated by reference above.

Referring to FIG. 8, conductive material 46 has been provided withincontact opening 40 in electrical connection with source/drain region 20through changed extending material 31 of substrate fragment 10.Exemplary preferred materials 46 include metals, conductive metalcompounds and/or conductively doped semiconductive material. Conductivematerial 46 might be the same as or different in composition from thatof changed extending material 31. Further by way of example only,conductive material 46 might be provided within contact opening 40before or after the exposing effective to transform extending material31 to a conductive material.

The above exemplary preferred and described embodiment was with respectto fabrication of a field effect transistor which was oriented generallyhorizontally relative to the substrate. By way of example only, FIG. 9depicts an alternate exemplary embodiment substrate fragment 10 dwherein a field effect transistor 16 d is oriented generally verticallyrelative to the substrate. Like numerals from the first describedembodiment are utilized where appropriate, with differences beingindicated with the suffix “d” or with different numerals. Transistorgate 28 d and gate dielectric material 26 d are depicted as comprisingan annulus formed about channel region 14 d. Source/drain region 20 dcomprises a semiconductive material projection 50 extending from channelregion 22 d. Projection 50 comprises a top surface 52 and side surfaces54 over which gate dielectric material 26 d (constituting an extension31 d thereof) is received. A contact opening 40 d has been formed withindielectric layer 38 d to at least a portion of gate dielectric material26 d extension 31 d received over top surface 52 of source/drain region20 d. Exposing such as described above in any of the other exemplaryembodiments has been conducted effective to transform extending portion31 d from a dielectric material to a conductive material.

The above-described exemplary preferred embodiments were with respect tomethods of forming a conductive contact to a source/drain region througha contact opening in a dielectric layer received over the transistorgate and at least one source/drain region of the transistor. However,the invention also contemplates methods of forming a conductive contactto a source/drain region of a field effect transistor independent ofsuch being conducted relative to a contact opening formed through adielectric layer received over a transistor gate and a source/drainregion. A preferred exemplary such method includes providing gatedielectric material intermediate a transistor gate and the channelregion of a field effect transistor. At least some of the gatedielectric material extends to be received over at least onesource/drain region of the field effect transistor. The gate dielectricmaterial received over the one source/drain region is exposed toconditions effective to change it from being electrically insulative tobe electrically conductive and in conductive contact with the onesource/drain region. Preferred attributes are otherwise as describedabove independent of the provision of a dielectric layer 38 and acontact opening 40 therein.

The invention also contemplates methods of forming a local interconnect.First exemplary preferred embodiments of the same are describedinitially with reference to FIGS. 10-14. A substrate fragment isindicated in FIGS. 10 and 11 generally with reference numeral 60. Suchis depicted as comprising a bulk semiconductor substrate 62 havingtrench isolation regions 64 formed therein. Preferred attributes areotherwise as described above in connection with the first embodiment,and of course semiconductor-on-insulator substrates and fabrication, aswell as other fabrication methods, are also contemplated whetherexisting or yet-to-be developed. Exemplary source/drain regions 66 and68 (complete or in process of fabrication) of different transistors inprocess are shown relative to substrate material 62. Exemplary gatelines 70 and 72 are shown received over channel regions (notspecifically designated with numerals) proximate source/drain regions 66and 68, respectively. Source/drain regions 66 and 68 can be consideredas first and second node regions, respectively, of semiconductorsubstrate 60. A gate dielectric material 74 has been providedintermediate at least one of transistor gates 70 and 72 to extendtherefrom to be received between first and second node regions 66 and68. In the depicted exemplary and preferred embodiment, gate dielectricmaterial 74 extends to be received over at least one of first and secondnode regions 66 and 68, with gate dielectric material 74, as shown,extending to be received over both such first and second node regions.

Referring to FIGS. 12 and 13, gate dielectric material 74 receivedbetween first and second node regions 66 and 68, respectively, has beenexposed to conditions effective to change it from being electricallyinsulative to being electrically conductive effective to form a localinterconnect 75 electrically connecting first node region 66 and secondnode region 68. Preferred attributes of conducting the same areotherwise as described above In connection with the above-describedother embodiments. Further by way of example only, one preferred mannerof defining interconnect outline 75 is by masking, for example utilizingphotoresist. By way of example only, FIG. 14 depicts a masking layer 73having been deposited and patterned to define the local interconnectoutlining 75 of FIGS. 12 and 13. Such may or may not be subsequentlyremoved if other than photoresist depending upon the material utilizedand the circuitry being fabricated, but will typically preferably beremoved.

The above-described exemplary method of forming a local interconnect waswhere first and second node regions 66 and 68 comprise a source/drainregion of one field effect transistor and a source/drain region ofanother field effect transistor. However, the invention alsocontemplates forming a local interconnect where one of the first andsecond node regions does not constitute any component of a field effecttransistor, including any source/drain region. Of course, the inventioncontemplates forming a local interconnect where one of the first andsecond node regions is a source/drain region of one transistor, and theother of the first and second node regions is a gate of anothertransistor. Further, the invention also contemplates neither of firstand second node regions 66 and 68 constituting any portion of a fieldeffect transistor. Regardless and by way of example only, either offirst and second node regions 66 and 68 might comprise any one orcombination of the same or different conductively doped semiconductivematerial and/or at least one of an elemental metal (which includesalloys of elemental metals) and a conductive metal compound.

By way of example only exemplary additional implementations of methodsof forming a local interconnect are described with reference to FIGS. 15and 16 in connection with a substrate fragment 80. Referring to FIG. 15,substrate fragment 80 comprises semiconductor material 82 (i.e.,monocrystalline silicon) having a dielectric layer 83 (i.e., BPSG)formed thereover. A conductive contact material 84 has been providedwithin dielectric layer 83, extending upwardly from semiconductivematerial 82. Exemplary first and second node regions 86 and 88,respectively, are depicted as being received within or on dielectriclayer 83. Preferred attributes are preferably as described above inconnection with the exemplary FIGS. 10-14 embodiment.

A capacitor 90 has been fabricated over dielectric layer 83. Suchcomprises a first capacitor electrode 92, a second capacitor electrode94 and a capacitor dielectric material 95 received therebetween.Exemplary preferred materials for capacitor dielectric 95 include thosedescribed above for gate dielectric material 26. At least some ofcapacitor dielectric material 95 extends to be received between firstand second node regions 86 and 88, respectively, of semiconductorsubstrate 80. In the depicted preferred embodiment, capacitor dielectricmaterial 96 extends to be received over at least one of first and secondnode regions 86 and 88, with capacitor dielectric material 95 beingreceived over both first and second node regions 86 and 88 in theexemplary embodiment.

Referring to FIG. 16, capacitor dielectric material 95 received betweenfirst and second node regions 86 and 88 has been exposed to conditionseffective to change it from being electrically insulative to beingelectrically conductive to form a local interconnect 98 whichelectrically connects first node region 86 and second node region 88.Preferred attributes for conducting the same are otherwise as describedabove in connection with the above-described embodiments.

The exemplary FIGS. 15 and 16 embodiment depicted formation of secondcapacitor electrode 94 prior to the exposing effective to form localinterconnect 98. Of course, the invention contemplates forming a secondcapacitor electrode after such exposing. For example, and by way ofexample only, FIG. 17 depicts an alternate embodiment substrate fragment80 a wherein local interconnect 98 has been fabricated prior to theformation of second electrode 94 of the FIGS. 15 and 16 embodiment.

The above exemplary embodiments of FIGS. 10-17 depict forming theoutline of the local interconnect before the exposing occurs. However,the invention also contemplates forming the outline of the localinterconnect after the exposing occurs. For example and by way ofexample only, all of the exposed of the gate dielectric material and/orthe capacitor dielectric material might be blanketly exposed toconditions effective to transform all of the same to a conductivematerial, followed by local interconnect patterning thereof (for exampleby photolithography and etch). Of course, the invention alsocontemplates exposing more than the ultimate local interconnect outline,but less than all the exposed gate dielectric material to theconditions, followed by local interconnect patterning thereof.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood; however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming a conductive metal suicide by reaction of metalwith silicon, comprising: providing a semiconductor substrate comprisingan exposed elemental silicon-containing surface; atomic layer depositingat least one of a nitride, boride, carbide, or oxide-comprising layeronto the exposed elemental silicon-containing surface to a thickness nogreater than 15 Angstroms; exposing the layer of thickness no greaterthan 15 Angstroms to plasma and depositing a conductive reaction layercomprising at least one of a first elemental metal or metal-richsilicide onto the plasma-exposed layer; and reacting said first metal ormetal-rich silicide of the conductive reaction layer with the elementalsilicon of the substrate effective to form a conductive metalsilicide-comprising contact region electrically connecting theconductive reaction layer with the substrate.
 2. The method of claim 1,wherein the atomic layer depositing is of a nitride-comprising layer. 3.The method of claim 2, wherein the nitride-comprising layer comprises anitride selected from the group consisting of tantalum nitride, titaniumnitride, tungsten nitride, boron nitride, aluminum nitride, hafniumnitride, and mixtures thereof.
 4. The method of claim 2, wherein thenitride-comprising layer is void of Si₃N₄.
 5. The method of claim 1,wherein the atomic layer depositing is of a boride-comprising layer. 6.The method of claim 5, wherein the boride-comprising layer comprises aboride selected from the group consisting of tungsten boride, titaniumboride, and mixtures thereof.
 7. The method of claim 1, wherein theatomic layer depositing is of a carbide-comprising layer.
 8. The methodof claim 7, wherein the carbide-comprising layer comprises a carbideselected from the group consisting of tantalum carbide, titaniumcarbide, silicon carbide, and mixtures thereof.
 9. The method of claim1, wherein the atomic layer depositing is of an oxide-comprising layer.10. The method of claim 9, wherein the oxide-comprising layer comprisesan oxide selected from the group consisting of rhodium oxide, rutheniumoxide, iridium oxide, and mixtures thereof.
 11. The method of claim 9,wherein the oxide-comprising layer is void of SiO₂.
 12. The method ofclaim 1, wherein the at least one of a nitride, boride, carbide, oroxide is of a second metal which is different from said first metal ofthe conductive reaction layer.
 13. The method of claim 1, wherein the atleast one of a nitride, boride, carbide, or oxide is of a second metalwhich is the same as said first metal of the conductive reaction layer.14. The method of claim 1, wherein the layer of thickness no greaterthan 15 Angstroms is of a thickness no less than 5 Angstroms.
 15. Themethod of claim 1, wherein the layer of thickness no greater than 15Angstroms is of a thickness from 5 Angstroms to 10 Angstroms.
 16. Themethod of claim 1, wherein the exposed elemental silicon-containingsurface comprises polycrystalline silicon.
 17. The method of claim 1,wherein the exposed elemental silicon-containing surface comprisesmonocrystalline silicon.
 18. The method of claim 17, wherein themonocrystalline silicon comprises epitaxially-grown silicon.
 19. Themethod of claim 1, wherein the exposing occurs during the depositing.20. The method of claim 1, wherein the exposing only occurs during thedepositing.
 21. The method of claim 1, wherein at least some of theexposing occurs prior to and separate from the depositing.
 22. Themethod of claim 21, wherein all of the exposing occurs prior to andseparate from the depositing.
 23. The method of claim 1, wherein theconductive reaction layer has an outer portion that at leastpredominately comprises said first elemental metal.
 24. The method ofclaim 23, wherein the conductive reaction layer outer portion consistsessentially of said first elemental metal.
 25. The method of claim 1,wherein the conductive reaction layer has an outer portion that at leastpredominately comprises said metal-rich silicide.
 26. The method ofclaim 25, wherein the conductive reaction layer outer portion consistsessentially of said metal-rich silicide.
 27. The method of claim 1,wherein the reacting occurs during the depositing.
 28. The method ofclaim 1, wherein the reacting occurs after the depositing.
 29. Themethod of claim 28, wherein the reacting does not occur during thedepositing.
 30. The method of claim 1, wherein the exposing and thereacting occur during the depositing.
 31. The method of claim 1, whereinthe deposited layer of thickness no greater than 15 Angstroms has anas-deposited resistance greater than 1000 microohms-cm, the exposing andreacting being effective to reduce resistance of the deposited layer ofthickness no greater than 15 Angstroms to less than 1000 microohms-cm.32. The method of claim 31, wherein the exposing and reacting areeffective to reduce resistance of the deposited layer of thickness nogreater than 15 Angstroms to less than 800 microohms-cm.
 33. The methodof claim 31, wherein: the layer of thickness no greater than 15Angstroms is of a thickness from 5 Angstroms to 10 Angstroms; theexposing occurs during the depositing; and the reacting occurs duringthe depositing.
 34. The method of claim 1, wherein the layer ofthickness no greater than 15 Angstroms comprises tantalum nitride. 35.The method of claim 34, wherein the conductive reaction layer comprisesat least one of titanium and titanium-rich titanium silicide.
 36. Themethod of claim 34, wherein the tantalum nitride is atomic layerdeposited from precursors comprising pentakis-dimethylamido-tantalum andammonia.
 37. The method of claim 34, wherein the layer of thickness nogreater than 15 Angstroms is of a thickness from 5 Angstroms to 10Angstroms.
 38. The method of claim 34, wherein the conductive reactionlayer has an outer portion that at least predominately comprises saidfirst elemental metal.
 39. The method of claim 34, wherein theconductive reaction layer has an outer portion that at leastpredominately comprises said metal-rich silicide.
 40. The method ofclaim 1, wherein the conductive metal silicide-comprising contact regionhas a thickness from 5 Angstroms to 100 Angstroms.
 41. The method ofclaim 1, wherein the exposing, depositing and reacting are effective toform all conductive metal silicide formed over the substrate by thereacting to have no more than 10% thickness variation as determined of athickest portion of said conductive metal silicide formed by thereacting.
 42. The method of claim 1, wherein the exposing, depositingand reacting are effective to form all conductive metal silicide formedover the substrate by the reacting to have no more than 1% thicknessvariation as determined of a thickest portion of said conductive metalsilicide formed by the reacting.
 43. The method of claim 1, wherein theexposing, depositing and reacting are effective to form all conductivemetal silicide formed over the substrate by the reacting to have from 1%to 3% thickness variation as determined of a thickest portion of saidconductive metal silicide formed by the reacting.
 44. The method ofclaim 1, wherein the conductive reaction layer is of a thickness whichis greater than that of the layer of thickness no greater than 15Angstroms.
 45. The method of claim 1, wherein the exposed elementalsilicon-containing surface is received within a contact opening formedwithin an insulative layer.
 46. A method of forming a conductive metalsilicide by reaction of metal with silicon, comprising: providing asemiconductor substrate comprising an exposed elementalsilicon-containing surface; atomic layer depositing a tantalumnitride-comprising layer onto the exposed elemental silicon-containingsurface to a thickness no greater than 15 Angstroms, the depositedtantalum nitride-comprising layer having a resistance greater than 1000microohms-cm; exposing the tantalum nitride-comprising layer ofthickness no greater than 15 Angstroms to plasma and depositing aconductive reaction layer comprising at least one of an elemental metalor metal-rich silicide onto the plasma-exposed layer; and reacting saidmetal or metal-rich silicide of the conductive reaction layer with theelemental silicon of the substrate effective to form a conductive metalsilicide-comprising contact region over the tantalum nitride-comprisinglayer which electrically connects the conductive reaction layer with thesubstrate; the exposing, depositing and reacting being effective toreduce resistance of the tantalum nitride-comprising layer to less than1000 microohms-cm.
 47. The method of claim 46, wherein the tantalumnitride-comprising layer as-deposited is of a thickness no less than 5Angstroms.
 48. The method of claim 46, wherein the tantalumnitride-comprising layer as-deposited is of a thickness from 5 Angstromsto 10 Angstroms.
 49. The method of claim 46, wherein the exposing occursduring the depositing.
 50. The method of claim 46, wherein the exposingonly occurs during the depositing.
 51. The method of claim 46, whereinat least some of the exposing occurs prior to and separate from thedepositing.
 52. The method of claim 51, wherein all of the exposingoccurs prior to and separate from the depositing.
 53. The method ofclaim 46, wherein the conductive reaction layer has an outer portionthat at least predominately comprises the elemental metal.
 54. Themethod of claim 46, wherein the conductive reaction layer has an outerportion that at least predominately comprises the metal-rich silicide.55. The method of claim 46, wherein the reacting occurs during thedepositing.
 56. The method of claim 46, wherein the reacting occursafter the depositing.
 57. The method of claim 56, wherein the reactingdoes not occur during the depositing.
 58. The method of claim 46,wherein the exposing and the reacting occur during the depositing. 59.The method of claim 46, wherein the exposing and reacting are effectiveto reduce resistance of the tantalum nitride-comprising layer to lessthan 800 microohms-cm.
 60. The method of claim 46, wherein: the layer ofthickness no greater than 15 Angstroms is of a thickness from 5Angstroms to 10 Angstroms; the exposing occurs during the depositing;and the reacting occurs during the depositing.
 61. The method of claim46, wherein the conductive metal silicide-comprising contact region hasa thickness from 5 Angstroms to 100 Angstroms.
 62. The method of claim46, wherein the exposing, depositing and reacting are effective to formall conductive metal silicide formed over the substrate by the reactingto have no more than 10% thickness variation as determined of a thickestportion of said conductive metal silicide formed by the reacting. 63.The method of claim 46, wherein the exposing, depositing and reactingare effective to form all conductive metal silicide formed over thesubstrate by the reacting to have no more than 1% thickness variation asdetermined of a thickest portion of said conductive metal silicideformed by the reacting.
 64. The method of claim 46, wherein theexposing, depositing and reacting are effective to form all conductivemetal silicide formed over the substrate by the reacting to have from 1%to 3% thickness variation as determined of a thickest portion of saidconductive metal silicide formed by the reacting.
 65. The method ofclaim 46, wherein the conductive reaction layer is of a thickness whichis greater than that of the tantalum nitride-comprising layer.
 66. Themethod of claim 46, wherein the exposed elemental silicon-containingsurface is received within a contact opening formed within an insulativelayer.